The present invention generally relates to semiconductor memory devices and more particularly to a semiconductor memory device having a current-mirror type amplifier for amplifying data outputted on a data bus.
Semiconductor memory devices generally have a memory cell array in which a number of memory cell transistors are arranged in rows and columns. In correspondence to each memory cell transistor, there is provided a memory cell capacitor for storing binary data in the form of electric charges. The memory cell transistors are connected to word lines extending in a row direction and bit lines extending in a column direction, and addressing of the memory cell is made by selecting one of the word lines and one of the bit lines.
When writing data, the data to be written is supplied to a bit line and transferred to a selected memory cell capacitor via a memory cell transistor by energizing a selected word line simultaneously. When reading data, on the other hand, the electric charges accumulated in a memory cell capacitor are transferred to a selected bit line via a memory cell transistor by energizing a selected word line. The minute change of voltage level thus induced on the bit line is detected and amplified by a sense amplifier.
In such semiconductor memory devices, various efforts are made to increase the speed of reading and writing. Among others, there is a technique to increase the speed of reading by amplifying the electric signals obtained on the bit line after amplification by a sense amplifier.
FIG. 1 shows a conventional semiconductor memory device that employs the foregoing construction for increasing the speed of reading.
Referring to FIG. 1, the semiconductor memory device includes a memory cell array 11 in which a number of memory cells 1a are arranged in rows and columns. Each memory cell 1a is connected to a pair of complementary bit lines BL, BL and a word line WL, wherein the bit lines are selectively enabled by a row decoder 14. The word lines, on the other hand, are enabled by a column decoder 13. Further, the column decoder 13 and the row decoder 14 are driven by an address buffer 15 that supplies a column selection signal to the column decoder 13 and a row selection signal to the row decoder 14 in response to address data ADDRESS supplied thereto.
To write data to the memory cell 1a in the memory cell array 11, an input buffer circuit 17 is used. The input buffer circuit 17 is supplied with input data Din and supplies the same to a complementary data bus line pair DB, DB in the form of complementary electric signals. The bus lines DB and DB are connected to the bit lines BL and BL via an input/output gate 12. The column decoder 13 controls the input/output gate 12 in response to the column selection signal supplied thereto, and the complementary electric signals on the data bus lines DB and DB are transferred to the selected bit line pair BL and BL. Thereby, the electric signals on the data bus lines DB and DB are transferred to the selected bit line pair BL and BL. Further, by selectively energizing the word line WL simultaneously, the electric signals on the selected bit line pair BL and BL are transferred to the memory cell 1a and stored therein in the form of electric charges.
When reading data, the row decoder 14 energizes a selected word line WL. Thereby, the memory cells connected to the selected word line WL transfer the electric charges stored therein to the respective bit line pairs BL, BL, and the minute voltage change caused in the bit lines is detected by a sense amplifier shown in FIG. 1 by the block 12 that is the same block for the input/output gate. The sense amplifier 12 supplies the output to the bit line pair BL and BL, and the electric voltages thus produced on a selected bit line pair are supplied to the complementary data bus DB, DB via the input/output gate 12. The voltage signals thus obtained on the data bus lines DB, DB are then outputted by an output buffer circuit 16 as output data Dout.
In order to accelerate the reading, there is provided a current-mirror type amplifier 2 between the data bus and the output buffer circuit 16 for amplifying the electric signals on the data bus DB, DB. By amplifying the level of the complementary signals on the data bus, the current mirror amplifier 2 enables a quick discrimination of the logic state of the data read from the memory cell 1a.
FIG. 2 shows a conventional current-mirror amplifier circuit together with a part of the memory cell array 11.
Referring to FIG. 2, the sense amplifier represented by SA in the drawing is provided in correspondence to each bit line pair BL and BL. Further, the bit lines BL and BL are connected respectively to the lines DB and DB of the data bus via transistors 12a and 12b forming the input/output gate 12. The transistors 12a and 12b are turned on in response to the high level state of the column selection signal represented as .phi..sub.A FIG. 2 and connect the bit lines to the corresponding lines of the data bus.
The electric signals thus transferred to the bus lines DB and DB are then passed through a limiter circuit 3. The limiter circuit 3 includes a first transistor Tr1 connected between a power supply line Vcc and the bit line BL and a second transistor Tr2 connected between the power supply line Vcc and the bit line BL. Each of the transistors Tr1 and Tr2 has a gate and a source connected with each other and is maintained always at the turned-on state. Thereby, a voltage drop corresponding to the threshold voltage of the transistors appears at the drain of the transistors, and the voltage of the data bus DB, DB is held at the level of Vcc-VthN, where VthN represents the threshold level of the transistors Tr1 and Tr2. For example, the voltage level of the data bus may be held at 4 volts, assuming the supply voltage Vcc of 5 volts and the threshold voltage VthN of 1 volt.
When there occurs a transfer of the electric signals from the bit lines BL and BL to the data bus lines DB and DB in response to the high level state of the column selection signal .phi..sub.A, the voltage level of the data bus DB, DB changes about the foregoing level of 4 volts, and this voltage change is detected by the current-mirror amplifier 2.
The current-mirror amplifier 2 includes two current-mirror amplifier circuits 2a and 2b having a similar construction, wherein the circuit 2a has a usual construction having a pair of P-channel MOSFETs Tr2a and Tr2b with respective gates connected with each other and respective drains connected commonly to the power supply line Vcc. As usual, the gate of the transistor Tr2b is connected to the source of the same transistor Tr2b. Further, the transistors Tr2a and Tr2b have respective sources connected to a source of an N-channel MOSFET Tr2c and a source of another N-channel MOSFET Tr2d. The transistor Tr2c in turn has a gate connected to the data bus line DB and a drain connected to a source of still other N-channel MOSFET Tr2e, while the transistor Tr2d has a gate connected to the data bus line DB and a drain connected to the source of the transistor Tr2e commonly to the drain of the transistor Tr2c. The transistor Tr2e has a gate to which an enable signal .phi..sub.B is supplied and a drain connected to the ground.
In operation of the circuit 2a, the transistor Tr2e is enabled in response to the enable signal .phi..sub.B. Further, the transistors Tr2c and Tr2d are supplied with the complementary input signals IN on the line DB and IN on the line DB. Thereby, the transistors Tr2c and Tr2d are caused to turn on and turn off in the complementary manner. As will be remarked later, the transistors Tr2c and Tr2d are not completely turned on or turned off in the foregoing operation.
In the current mirror amplifier 2a, an output current flows through the transistor Tr2a when a current flows through the transistor Tr2b such that the magnitude of the output current through the transistor Tr2a is equal to the magnitude of the current through the transistor Tr2b. The current through the transistor Tr2b will be referred to as the reference current. Thus, when the transistor Tr2d is turned on in response to the high level state of the complementary input signal IN on the data bus line DB, the reference current flows through the transistor Tr2b and an output current flows through the transistor Tr2a accordingly. As the transistor Tr2c is in the turned-off state in response to the low level state of the input signal IN on the data bus line DB, the output current flowing through the transistor Tr2a is mostly diverted to an output bus OUT that is connected to the source of the transistor Tr2c. Thereby, the voltage level of the bus OUT increases to a level close to Vcc.
The other current-mirror amplifier 2b has a similar construction except that the transistors Tr2a and Tr2b are reversed. Thus, a transistor Tr2b' that corresponds to the transistor Tr2b and having a gate and a source connected with each other, is connected in series to a transistor Tr2c' that corresponds to the transistor Tr2c and having a gate to which the input signal IN is supplied from the data bus line DB. Similarly, a transistor Tr2a' corresponding to the transistor Tr2a is connected in series to a transistor Tr2d'. Further, a complementary output bus OUT is connected to the source of the transistor Tr2d'.
Thus, in the previous case where the transistor Tr2d is turned on and the output current supplied to the output bus OUT via the transistor Tr2a, only small current flows through the transistor Tr2a' in correspondence to the turning-off of the transistor Tr2c' that in turn is caused simultaneously to the turning-off of the transistor Tr2c. Further, the transistor Tr2d' is turned on simultaneously to the turning-on of the transistor Tr2d and the voltage level on the output bus OUT becomes low. In other words, a small output current is obtained on the bus OUT and the voltage level on the bus OUT approaches to zero. In the case where the input signal IN on the bus DB has the high level state, on the other hand, an output current is obtained on the bus OUT while only a small output current is obtained on the bus OUT. Thus, the level of the output bus OUT approaches to zero while the level of the bus OUT approaches to Vcc.
FIG. 3 shows the reading operation of the semiconductor memory device of FIG. 1 wherein the circuit of FIG. 2 is used.
Referring to FIG. 3, the column selection signal .phi..sub.A rises first in response to the selection of the bit line pair BL and BL. In response to the rising of the signal .phi..sub.A, the electric signals on the selected bit line pair are transferred to the data bus DB, DB as illustrated. Next, the activation signal .phi..sub.B is supplied as illustrated, and the current-mirror circuit 2 produces the output signals on the output bus OUT, OUT, wherein the level of the bus OUT is lowered with respect to the level of the bus OUT.
It should be noted that, in the foregoing operation of the current-mirror amplifier, the transistors Tr2c and Tr2d are not completely turned on or turned off even when the level of the signals on the bus lines DB and DB has changed to the high level or low level. By setting the operation of the current-mirror amplifier 2 as such, one can reduce the time needed to turn over of the logic state of the output signals on the output bus OUT, OUT.
In order to achieve the foregoing optimum operation, the data bus lines DB and DB are biased by the limiter circuit 3 at a predetermined level that is determined by the threshold voltage of the transistors Tr1 and Tr2. Thereby, the limiter circuit 3 limits the voltage swing of the signals IN and IN on the data bus DB, DB such that the transistors Tr2c and Tr2d are not completely turned on or turned off. The optimum operational point of the current-mirror amplifier 2 is determined based upon various factors such as the speed of reading and the gain of amplification. For example, the current-mirror amplifier circuit 2 provides the highest speed and gain when the data bus lines DB and DB are biased at the level Vcc/2.
In the foregoing conventional circuit of FIG. 2 where only a single transistor is used between the supply voltage line and either bus lines, the data bus lines DB and DB are biased inevitably at the level of about 4 volts, assuming the threshold voltage of 1 volt. In such a case, therefore, the current mirror circuit 2 is not optimized with respect to the speed and gain. Particularly, when the level of the voltage Vcc is increased to Vcc' as shown in FIG. 4, the speed and gain of the current-mirror amplifier is deteriorated further. It should be noted that the data bus lines DB and DB are biased at relatively high voltage level of 4 volts. Thus, when there is a voltage increase of 1 volt in the supply voltage Vcc, the biasing level of the data bus lines DB and DB will increase from 4 volts to 5 volts. Thereby, the deviation in the operational point from the optimum level of Vcc/2 increases further.
FIG. 5 shows a conventional construction to optimize the operation of the current-mirror amplifier.
Referring to FIG. 5, a limiter circuit 3' is used in place of the limiter circuit 3, in which transistors Tr3 and Tr4 are connected in series and interposed between the power supply line Vcc and the data bus DB line. Similarly, transistors Tr5 and Tr6 are connected in series and interposed between the power supply line Vcc and the data bus DB line. In this construction, the voltage drop caused by the limiter circuit 3' becomes about 2 volts.
FIG. 6 shows the operation of the semiconductor memory device of FIG. 1 in which the limiter circuit 3' is used in place of the limiter circuit 3. As can be seen in this drawing, the data bus DB, DB is biased at about 3 volts assuming the threshold voltage VthN of 1 volt, and an optimum amplification is achieved in the current-mirror amplifier 2, with respect to the speed and gain.
This conventional construction, however, has a problem of unreliable operation of the current-mirror amplifier. More specifically, when there is a voltage drop in the supply voltage Vcc, there is a risk that the voltage level of the data bus DB, DB decreases excessively. For example, when the supply voltage Vcc is decreased to about 4 volts, the biasing level of the data bus decreases to about 2 volts. Thereby, there is a substantial risk that the current-mirror amplifier 2 does not operate when the signals IN and IN are supplied to the respective bus lines DB and DB. It should be noted that such a voltage drop or negative voltage bump of the supply voltage Vcc tends to occur relatively often, for example at the time of reading data where the sense amplifiers SA are activated. It should be noted that the sense amplifiers SA for the entire memory cell columns are activated simultaneously when reading data.
The foregoing construction of FIG. 5, using the series connection of the MOS transistors Tr3 and Tr4 or Tr5 and Tr6 in the limiter circuit 3', has another problem of increased variation in the biasing level of the bus lines. It should be noted that the biasing level of the bus lines DB and DB is determined by the sum of the threshold voltage of the transistors that are connected in series, while there is a substantial scattering in the threshold voltage VthN in the MOS transistors that are available at present. Thereby, the variation in the biasing level is further enhanced. In the circuit 3', therefore, the risk of the current-mirror amplifier 2 becoming inoperational due to the momentary drop of the supply voltage Vcc may be enhanced because of the increased scattering of the bias voltage.